A 74HC4060 HCMOS oscillator/divider integrated circuit (IC1)was chosen for generating the master clock Choosing that part lets us use an inexpensive 4-MHz crystal The divide－by－16 output of IC1, at 250 kHz, is applied to a Motorola MC100EL32 divide-by－2 ECLips flip－flop (IC2) through level shift and decoupling components C7.015, and R6 Resistor R3 sets the input impedance seel1 by IC2 and divides the amplitude of IC1's output down to the ECLips input levels The MC100EL32 has transition times of both outputs specified at less than 350 ps (0.35 ns)and temperature-compensated output levels The divide－by－2 action of the device provides 125 kHz at approximately 800 mV p-p to the amplitude adjustment circuit and output stage. The output of IC2 is terminated with loads consisting of resistor pairs R1-R4 and R2-R5. The values shown provide an equivalent load voltage of about -2 V and a load impedance of 50 Ω. The output of IC2 is ac-coupled by capacitors C12, C13, C14, and C16 to an adjustable T-attenuator network. The various values of the coupling capacitors combine to transmit the fat rise-time edges (C12 and C13) while preventing droop at the 125-kHz base frequency (C14 and C16).
Required Field 
